SEMINAR OF
THE APPLIED PHYSICS SCIENTIFIC SECTION




2009 Academic Year

Wednesday, 4 November 2009

Oppenheimer Meeting Room, Second Floor, Leonardo Building


Time: 15.30


Hardware Implementation of Particle Filters (*)

 
Imbaby I. Mahmoud (**), (***)
Atomic Energy Authority, NRC, Engineering Department, Cairo, Egypt







(*) Summary:  An efficient H/W implementation of Sample Important Resample (SIR) Particle Filters (PF) is presented. Apart from PFs which do not use resampling, SIR PF has less computational complexity. Resampling is not computationally intensive but it is a bottleneck in parallel implementation. To increase speed we modified the algorithm to allow for overlapping its operations with particle generation. We used multiple processing elements (PEs) to work in parallel, where each PE processes a fraction of the total number of particles, and a single Resampling and Routing Unit (RRU), which controls the operations of the PEs, making inter-resampling and propagating allocated particles for PEs. The modifications presented here concerned with both sampling and resampling steps. The generation of new particles, the computation of their weights and intra-resampling are processed in parallel using 8 PEs, which each process eight particles. To distribute resampled particles equally, the routing unit compares the amount of particles allocated for each PE and exchange particles among PEs using a local ring. If one PE unit allocated the maximum number of particles (i.e. 8 particles), the routing unit escapes it and allocates the rest of particles to the next PE until it reaches the maximum amount of particles and so on. Routing strategy presented here allows for efficient memory utilization in addition to resource saving. For weight computation step, a linear function is proposed instead of exponential one. This decreases the complexity of the architecture without degrading the results. The H/W implementation targeted an Enhanced PF for object tracking application. FPGA is used as implementation H/W platform.

____________________________________________________
_________________
(**) Biodata Professor Imbaby I. Mahmoud is Head of the Computer and System Engineering Department, NRC, Atomic Energy Authority, Cairo, Egypt. He earned his Dr. of Engeneering Degree from School of Science and Engineering, Waseda University, Tokyo, Japan in March 1994 in the field of Very Large Scale Integration Design.

He worked at the KFKI, Hungarian Academy of Sciences, Budapest, Hungary under an IAEA fellowship in 1998. In addition he has served as technical officer of an IAEA project on Environmental Monitoring Instruments.

During the period Oct.2001–Jun2007 Professor Mahmoud lectured on programming, computer logic, computer networks and collaborated with graduation projects at Dammam College of Technology in Saudi Arabia. In the same period he supervised M. Sc. and Ph. D. candidates in Egypt in the field of design and implementation of different algorithms in Field Programmable Gate Array.

Professor Mahmoud is a member of several scientific associations including The Institute of Electronics, Information and Communication Engineers, Japan, IEEE, USA,and the Egyptian Society of Nuclear Sciences and Applications.


____________________________________________________ _________________

(***) From work by H. A. Abd El-Halym , Imbaby I. Mahmoud, and S. E.-D. Habib.